Research Projects

All the research projects that the Space Technology Centre has been involved in are described below:

Robust Entry Descent and Landing System for ExoMars

FEIC feature tracking on a PANGU generated image sequence

The Robust Entry Descent and Landing System (EDLS) for ExoMars study aims to develop technologies to ensure a safe landing of ExoMars on the surface of Mars. The overall project is being led by LogicaCMG.

The overall project objectives are to:

  • Assess a number of novel but pragmatic and achievable candidate methodologies to:
    • Improve the accuracy of a landing from ballistic entry.
    • Reduce the risk of mission failure during the terminal phase.
  • Quantify the impact of key atmospheric variables on the propagation of the injection covariance matrix during entry, descent and landing thereby allowing:
    • A more rigorous approach to be taken to the design of the overall EDLS solution
    • Novel methods for accuracy improvement and risk reduction to be developed in a realistic environment

The principal objective for the University of Dundee was to:

  • Investigate processing of sensor data to estimate the transverse velocity of the lander.

SpaceWire Router ESM006

Details coming soon.

VINSE: Vision-Based Integrated Navigation for Space Exploration

The VINSE (Vision-Based Integrated Navigation for Space Exploration) activity is an EU Marie Curie Outgoing International Fellowship. The Research Fellow is Dr Victor Silva, a former PhD student in the Space Technology Centre at Dundee. Victor is funded to work for two years at the NASA Jet Propulsion Laboratory (JPL) and to then return to Dundee for another year. His research intends to show that the integration/fusion of visual information with inertial measurements can provide robust surface relative navigation suitable for planetary lander missions to many different planetary bodies. The objectives will be achieved through the international collaboration with the JPL, the World’s leading organization on technology for planetary landers and robotic space exploration, and the UoD (University of Dundee), Europe’s leading organization on planet surface and sensor simulation for testing planetary landers.


The LIDAR-ILT research was done as a sub-contractor to EADS Astrium SAS. The aim of this work was to extend PANGU scanning LIDAR sensor to support a different type of scanning pattern designed for a surface rover vehicle. In contrast to the original LIDAR-GNC scanner, the ILT system performs sinusoidal scans on sub-windows of the full field of view.

After each scan is completed the system moves to an adjacent sub-window and scans in the opposite direction to minimise scanner movement. Within each scanning window the horizontal motion of the laser varies sinusoidally while the vertical motion is linear. Although each scan is expected to take several seconds in real time, the sensor simulation takes into account spacecraft motion during the scanning interval. PANGU models and the LIDAR simulation have been integrated in a guidance and navigation control system prototype by Astrium.

SpaceWire CODEC IP - Actel Implementation

The SpaceWire CODEC IP Actel implementation is an ESA managed project to provide an implementation of the SpaceWire CODEC IP VHDL model to the Actel RTAX and RTSX FPGA series devices. The Actel RTAX and RTSX devices are radiation tolerant versions of the AX and SX commercial FPGAs which provide protection against single event effects (SEE). RTAX and SX devices use anti-fuse (program once) technology, are protected from single event latch-up (SEL) and implement triple mode redundancy for each internal flip-flop to protect against single event upsets (SEU).


Details coming soon.

Real-Time Embedded CORBA over SpaceWire (RECS)

To investigate effective DSP processor to SpaceWire integration, the University of Dundee has developed a DSP board using one of the latest DSP processors from Analog Devices and a SpaceWire router. The SpaceWire DSP board comprises an eight-port SpaceWire router connected to an Analog Devices 21160 SHARC (Super-Harvard ARChitecture) DSP processor. The 21160 processor has six SHARC links which are high-speed, half-duplex, bi-directional, point-to-point communication links designed to connect together several SHARC processors in a parallel processing array. These links form the bridge between the SHARC processor and the SpaceWire router. Data to be sent out from the DSP processor are formed into SpaceWire packets with an appropriate destination address header and the cargo (i.e. the data to be sent in the packet). The packet is then transmitted across the SHARC link to the SpaceWire router with an end of packet marker code being appended to the packet. Data is received in a similar way with the SpaceWire packet being transferred across the SHARC link.

Proof of Concept for "Software Developer's Right Hand"

The Software Developer's Right Hand is an innovative software development support environment which aims to improve software development productivity, software quality and software maintainability, and with automated documentation support. The project is funded by Scottish Enterprise through their Proof of Concept Programme.

SpaceWire Router ETD031

Details coming soon.

Multi-Purpose Vision Navigation

Details coming soon.